1. Field
The present invention generally relates to semiconductor devices and structures for integrated circuits, and, more particularly, to methods for etching dielectric layers comprising silicon and nitrogen.
2. Description of Related Art
Semiconductor device geometries have dramatically decreased in size since their introduction several decades ago. Modern semiconductor fabrication equipment routinely produces devices with 250 nm, 180 nm, and 65 nm feature sizes, and new equipment is being developed and implemented to make devices with even smaller geometries. The smaller sizes, however, mean device elements have to work together in closer proximity to each other, which can increase the chances of electrical interference, including cross-talk and parasitic capacitance.
To reduce the degree of electrical interference, dielectric insulating materials are used to fill the gaps, trenches, and other spaces between the device elements, metal lines, and other device features. The dielectric materials are chosen for their ease of formation in the spaces between device features, and their low dielectric constants (i.e., “k-values”). Dielectrics with lower k-values are better at minimizing cross-talk and RC time delays, as well as reducing the overall power consumption of the device. One commonly-used dielectric material is silicon oxide.
Additionally, during the formation of semiconductor devices, silicon nitride dielectric films have been used as barriers or etch stop layers in various applications and may be formed adjacent to or proximate silicon oxide layers. Silicon nitride dielectric films may provide a desired protection for structures such as transistor gates, or metal contacts lying thereunder. During fabrication, dry chemical processes may be utilized in contact cleaning steps or a clean step prior to subsequent processing, such as, the formation of a silicide layer on the substrate. These conventional processes require the silicon oxide cleaning chemicals to adsorb or condense onto the surface of the wafer. However, lower condensation proximate a contact hole or trench bottom, as compared to the top (near the wafer surface) leads to lower silicon oxide removal at the contact hole (or trench) bottom than at the top surface. For pre-silicide and contact clean applications, the above processes have high oxide/silicon nitride etch selectivity.
However, for some applications, it is required to etch the silicon nitride. For example, if there is some residual silicon nitride left at the contact surface, the aforementioned high selectivity processes cannot be used to clean the silicon nitride from the surface without damaging the oxide layer. In other examples, even higher silicon nitride etch selectivity to oxide may be required. For example, for shallow trench isolation (STI) trench clean applications prior to the deposition of a silicon oxide liner, high silicon oxide to silicon nitride etch selectivity processes may cause an overhang to be formed near the top of the trench by undercutting the pad oxide layer below the silicon nitride layer, thereby forming trench defects after the trench fill.
Thus, there is a need in the art for improved etch processes for etching silicon nitride materials.